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www.powerint.com february 2009 tny263-268 tinyswitch-ii family enhanced, energy ef cient, low power off-line switcher ? figure 1. typical standby application. product highlights tinyswitch-ii features reduce system cost fully integrated auto-restart for short circuit and open loop fault protection C saves external component costs built-in circuitry practically eliminates audible noise with ordinary dip-varnished transformer programmable line undervoltage detect feature prevents power on/off glitches C saves external components frequency jittering dramatically reduces emi (~10 db) C minimizes emi ? lter component costs 132 khz operation reduces transformer size C allows use of ef12.6 or ee13 cores for low cost and small size very tight tolerances and negligible temperature variation on key parameters eases design and lowers cost lowest component count switcher solution expanded scalable device family for low system cost better cost/performance over rcc & linears lower system cost than rcc, discrete pwm and other integrated/hybrid solutions cost effective replacement for bulky regulated linears simple on/off control C no loop compensation needed no bias winding C simpler, lower cost transformer simple design practically eliminates rework in manufacturing ecosmart ? C extremely energy ef? cient no load consumption <50 mw with bias winding and <250 mw without bias winding at 265 vac input meets california energy commission (cec), energy star, and eu requirements ideal for cell-phone charger and pc standby applications high performance at low cost high voltage powered C ideal for charger applications high bandwidth provides fast turn on with no overshoot current limit operation rejects line frequency ripple built-in current limit and thermal protection improves safety description tinyswitch-ii integrates a 700 v power mosfet, oscillator, high voltage switched current source, current limit and thermal shutdown circuitry onto a monolithic device. the start-up and operating power are derived directly from the voltage on the drain pin, eliminating the need for a bias winding and associated circuitry. in addition, the tinyswitch-ii devices incorporate auto-restart, line undervoltage sense, and frequency jittering. an innovative design minimizes audio frequency components in the simple on/off control scheme to practically eliminate audible noise with standard taped/varnished ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pi-2684-021809 wide-range hv dc input d s en/uv bp + - + - dc output tinyswitch-ii optional uv resistor transformer construction. the fully integrated auto-restart circuit safely limits output power during fault conditions such as output short circuit or open loop, reducing component count and secondary feedback circuitry cost. an optional line sense resistor externally programs a line undervoltage threshold, which eliminates power down glitches caused by the slow discharge of input storage capacitors present in applications such as standby supplies. the operating frequency of 132 khz is jittered to signi? cantly reduce both the quasi-peak and average emi, minimizing ? ltering cost. output power table product 3 230 vac 15% 85-265 vac adapter 1 open frame 2 adapter 1 open frame 2 tny263 p/g 5 w 7.5 w 3.7 w 4.7 w tny264 p/g 5.5 w 9 w 4 w 6 w tny265 p/g 8.5 w 11 w 5.5 w 7.5 w tny266 p/g 10 w 15 w 6 w 9.5 w tny267 p/g 13 w 19 w 8 w 12 w tny268 p/g 16 w 23 w 10 w 15 w table 1. output power table. notes: 1. minimum continuous power in a typical non-ventilated enclosed adapter measured at 50 c ambient. 2. minimum practical continuous power in an open frame design with adequate heat sinking, measured at 50 c ambient (see key applications considerations). 3. packages: p: dip-8b, g: smd-8b. please see part ordering information.
rev. h 02/09 2 tny263-268 www.powerint.com figure 2. functional block diagram. figure 3. pin con? guration. pin functional description drain (d) pin: power mosfet drain connection. provides internal operating current for both start-up and steady-state operation. bypass (bp) pin: connection point for a 0.1 f external bypass capacitor for the internally generated 5.8 v supply. enable/undervoltage (en/uv) pin: this pin has dual functions: enable input and line undervoltage sense. during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is terminated when a current greater than 240 a is drawn from this pin. this pin also senses line undervoltage conditions through an external resistor connected to the dc line voltage. if there is no external resistor connected to this pin, tinyswitch-ii detects its absence and disables the line undervoltage function. source (s) pin: control circuit common, internally connected to output mosfet source. source (hv rtn) pin: output mosfet source connection for high voltage return. pi-2643-030701 clock oscillator 5.8 v 4.8 v source (s) s r q dc max bypass (bp) + - v i limit fault present current limit comparator enable leading edge blanking thermal shutdown + - drain (d) regulator 5.8 v bypass pin under-voltage 1.0 v + v t enable/ under- voltage (en/uv) q 240 m a50 m a line under-voltage reset auto- restart counter jitter 1.0 v 6.3 v current limit state machine pi-2685-101600 en/uv d s s s (hv rtn) s (hv rtn) bp p package (dip-8b) g package (smd-8b) 8 5 7 1 4 2 3
rev. h 02/09 3 tny263-268 www.powerint.com figure 4. frequency jitter. tinyswitch-ii functional description tinyswitch-ii combines a high voltage power mosfet switch with a power supply controller in one device. unlike conventional pwm (pulse width modulator) controllers, tinyswitch-ii uses a simple on/off control to regulate the output voltage. the tinyswitch-ii controller consists of an oscillator, enable circuit (sense and logic), current limit state machine, 5.8 v regulator, bypass pin undervoltage circuit, over- temperature protection, current limit circuit, leading edge blanking and a 700 v power mosfet. tinyswitch-ii incorporates additional circuitry for line undervoltage sense, auto-restart and frequency jitter. figure 2 shows the functional block diagram with the most important features. oscillator the typical oscillator frequency is internally set to an average of 132 khz. two signals are generated from the oscillator: the maximum duty cycle signal (dc max ) and the clock signal that indicates the beginning of each cycle. the tinyswitch-ii oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 8 khz peak-to-peak, to minimize emi emission. the modulation rate of the frequency jitter is set to 1 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter should be measured with the oscilloscope triggered at the falling edge of the drain waveform. the waveform in figure 4 illustrates the frequency jitter of the tinyswitch-ii. enable input and current limit state machine the enable input circuit at the en/uv pin consists of a low impedance source follower output set at 1.0 v. the current through the source follower is limited to 240 a. when the current out of this pin exceeds 240 a, a low logic level (disable) is generated at the output of the enable circuit. this enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. if high, the power mosfet is turned on for that cycle (enabled). if low, the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the en/uv pin voltage or current during the remainder of the cycle are ignored. the current limit state machine reduces the current limit by discrete amounts at light loads when tinyswitch-ii is likely to switch in the audible frequency range. the lower current limit raises the effective switching frequency above the audio range and reduces the transformer ? ux density, including the associated audible noise. the state machine monitors the sequence of en/uv pin voltage levels to determine the load condition and adjusts the current limit level accordingly in discrete amounts. under most operating conditions (except when close to no- load), the low impedance of the source follower keeps the voltage on the en/uv pin from going much below 1.0 v in the disabled state. this improves the response time of the optocoupler that is usually connected to this pin. 5.8 v regulator and 6.3 v shunt voltage clamp the 5.8 v regulator charges the bypass capacitor connected to the bypass pin to 5.8 v by drawing a current from the voltage on the drain pin whenever the mosfet is off. the bypass pin is the internal supply voltage node for the tinyswitch-ii. when the mosfet is on, the tinyswitch-ii operates from the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows tinyswitch-ii to operate continuously from current it takes from the drain pin. a bypass capacitor value of 0.1 f is suf? cient for both high frequency decoupling and energy storage. in addition, there is a 6.3 v shunt regulator clamping the bypass pin at 6.3 v when current is provided to the bypass pin through an external resistor. this facilitates powering of tinyswitch-ii externally through a bias winding to decrease the no-load consumption to about 50 mw. bypass pin undervoltage the bypass pin undervoltage circuitry disables the power mosfet when the bypass pin voltage drops below 4.8 v. once the bypass pin voltage drops below 4.8 v, it must rise back to 5.8 v to enable (turn-on) the power mosfet. over temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is typically set at 135 c with 70 c hysteresis. when the die temperature rises above this threshold the power mosfet is disabled and remains disabled until the die temperature falls by 70 c, at which point it is re-enabled. a large hysteresis of 70 c (typical) is provided to prevent overheating of the pc board due to a continuous fault condition. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of 600 0510 136 khz 128 khz v drain time ( s) pi-2741-041901 500 400 300 200 100 0
rev. h 02/09 4 tny263-268 www.powerint.com figure 5. tinyswitch-ii auto-restart operation. pi-2699-030701 0 1000 2000 time (ms) 0 5 0 10 100 200 300 v drain v dc-output that cycle. the current limit state machine reduces the current limit threshold by discrete amounts under medium and light loads. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and secondary- side recti? er reverse recovery time will not cause premature termination of the switching pulse. auto-restart in the event of a fault condition such as output overload, output short circuit, or an open loop condition, tinyswitch-ii enters into auto-restart operation. an internal counter clocked by the oscillator gets reset every time the en/uv pin is pulled low. if the en/uv pin is not pulled low for 50 ms, the power mosfet switching is normally disabled for 850 ms (except in the case of line undervoltage condition, in which case it is disabled until the condition is removed). the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. figure 5 illustrates auto-restart circuit operation in the presence of an output short circuit. in the event of a line undervoltage condition, the switching of the power mosfet is disabled beyond its normal 850 ms time until the line undervoltage condition ends. line undervoltage sense circuit the dc line voltage can be monitored by connecting an external resistor from the dc line to the en/uv pin. during power-up or when the switching of the power mosfet is disabled in auto-restart, the current into the en/uv pin must exceed 49 a to initiate switching of the power mosfet. during power-up, this is accomplished by holding the bypass pin to 4.8 v while the line undervoltage condition exists. the bypass pin then rises from 4.8 v to 5.8 v when the line undervoltage condition goes away. when the switching of the power mosfet is disabled in auto-restart mode and a line undervoltage condition exists, the auto-restart counter is stopped. this stretches the disable time beyond its normal 850 ms until the line undervoltage condition ends. the line undervoltage circuit also detects when there is no external resistor connected to the en/uv pin (less than ~2 a into the pin). in this case the line undervoltage function is disabled. tinyswitch-ii operation tinyswitch-ii devices operate in the current limit mode. when enabled, the oscillator turns the power mosfet on at the beginning of each cycle. the mosfet is turned off when the current ramps up to the current limit or when the dc max limit is reached. since the highest current limit level and frequency of a tinyswitch-ii design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. if the tinyswitch-ii is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the dc max limit is reached. enable function tinyswitch-ii senses the en/uv pin to determine whether or not to proceed with the next switching cycle as described earlier. the sequence of cycles is used to determine the current limit. once a cycle is started, it always completes the cycle (even when the en/uv pin changes state half way through the cycle). this operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback. the en/uv pin signal is generated on the secondary by comparing the power supply output voltage with a reference voltage. the en/uv pin signal is high when the power supply output voltage is less than the reference voltage. in a typical implementation, the en/uv pin is driven by an optocoupler. the collector of the optocoupler transistor is connected to the en/uv pin and the emitter is connected to the source pin. the optocoupler led is connected in series with a zener diode across the dc output voltage to be regulated. when the output voltage exceeds the target regulation voltage level (optocoupler led voltage drop plus zener voltage), the optocoupler led will start to conduct, pulling the en/uv pin low. the zener diode can be replaced by a tl431 reference circuit for improved accuracy. on/off operation with current limit state machine the internal clock of the tinyswitch-ii runs all the time. at the beginning of each clock cycle, it samples the en/uv pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines
rev. h 02/09 5 tny263-268 www.powerint.com v drain v en clock d drain i max pi-2749-050301 figure 6. tinyswitch-ii operation at near maximum loading. v drain v en clock d drain i max pi-2667-090700 figure 8. tinyswitch-ii operation at medium loading. pi-2377-091100 v drain v en clock d drain i max figure 7. tinyswitch-ii operation at moderately heavy loading. the appropriate current limit. at high loads, when the en/uv pin is high (less than 240 a out of the pin), a switching cycle with the full current limit occurs. at lighter loads, when en/uv is high, a switching cycle with a reduced current limit occurs. at near maximum load, tinyswitch-ii will conduct during nearly all of its clock cycles (figure 6). at slightly lower load, it will skip additional cycles in order to maintain voltage regulation at the power supply output (figure 7). at medium loads, cycles will be skipped and the current limit will be reduced (figure 8). at very light loads, the current limit will be reduced even further (figure 9). only a small percentage of cycles will occur to satisfy the power consumption of the power supply. the response time of the tinyswitch-ii on/off control scheme is very fast compared to normal pwm control. this provides tight regulation and excellent transient response. power up/down the tinyswitch-ii requires only a 0.1 f capacitor on the bypass pin. because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically 0.6 ms. due to the fast nature of the on/off feedback, there is no overshoot at the power supply output. when an external resistor (2 m ) is connected from the positive dc input to the en/uv pin, the power mosfet switching will be delayed during power-up until the dc line voltage exceeds the threshold (100 v). figures 10 and 11 show the power-up timing waveform of tinyswitch-ii in applications with and without an external resistor (2 m ) connected to the en/uv pin. during power-down, when an external resistor is used, the power mosfet will switch for 50 ms after the output loses regulation. the power mosfet will then remain off without any glitches since the undervoltage function prohibits restart when the line voltage is low. figure 12 illustrates a typical power-down timing waveform of tinyswitch-ii. figure 13 illustrates a very slow power-down timing waveform of tinyswitch-ii as in standby applications. the external resistor (2 m ) is connected to the en/uv pin in this case to prevent unwanted restarts. the tinyswitch-ii does not require a bias winding to provide power to the chip, because it draws the power directly from the drain pin (see functional description above). this has
rev. h 02/09 6 tny263-268 www.powerint.com figure 12. normal power-down timing (without uv). figure 13. slow power-down timing with optional external (2 m ) uv resistor connected to en/uv pin. figure 10. tinyswitch-ii power-up with optional external uv resistor (2 m ) connected to en/uv pin. figure 11. tinyswitch-ii power-up without optional external uv resistor connected to en/uv pin. pi-2661-072400 v drain v en clock d drain i max figure 9. tinyswitch-ii operation at very light load. two main bene? ts. first, for a nominal application, this eliminates the cost of a bias winding and associated components. secondly, for battery charger applications, the current-voltage characteristic often allows the output voltage to fall close to zero volts while still delivering power. this type of application normally requires a forward-bias winding which has many more associated components. with tinyswitch-ii, neither are necessary. for applications that require a very low no-load power consumption (50 mw), a resistor from a bias winding to the bypass pin can provide the power to the chip. the minimum recommended current supplied is 750 a. the bypass pin in this case will be clamped at 6.3 v. this method will eliminate the power draw from the drain pin, thereby pi-2395-030801 0 2.5 5 time (s) 0 100 200 400 300 0 100 200 v dc-input v drain 0 12 time (ms) 0 200 400 5 0 10 0 100 200 pi-23 8 3-030 8 01 v dc-input v bypass v drain pi-2381-1030801 0 12 time (ms) 0 200 400 5 0 10 0 100 200 v dc-input v bypass v drain pi-2348-030801 0 .5 1 time (s) 0 100 200 300 0 100 200 400 v dc-input v drain
rev. h 02/09 7 tny263-268 www.powerint.com figure 14. 2.5 w constant voltage, constant current battery charger with universal input (85-265 vac). pi-2706-021809 + 5 v 500 ma rtn d1 1n4005 c1 3.3 f 400 v fusible rf1 8.2 c3 0.1 f c7 10 f 10 v 8 5-265 vac l1 2.2 mh d2 1n4005 d3 1n4005 d4 1n4005 r2 200 k u2 ltv817 d5 1n5819 shield l2 3.3 h c5 330 f 16 v c2 3.3 f 400 v c6 100 f 35 v r7 100 r4 1.2 1/2 w q1 2n3904 r8 270 vr1 bzx79- b3v9 3.9 v u1 tny264 c3 2.2 nf d6 1n4937 r6 1 1/2 w t1 r1 1.2 k 1 8 4 5 r3 22 r9 47 c8 680 pf y1 safety tinyswitch-ii d s bp en/uv reducing the no-load power consumption and improving full- load ef? ciency. current limit operation each switching cycle is terminated when the drain current reaches the current limit of the tinyswitch-ii. current limit operation provides good line ripple rejection and relatively constant power delivery independent of input voltage. bypass pin capacitor the bypass pin uses a small 0.1 f ceramic capacitor for decoupling the internal power supply of the tinyswitch-ii. application examples the tinyswitch-ii is ideal for low cost, high ef? ciency power supplies in a wide range of applications such as cellular phone chargers, pc standby, tv standby, ac adapters, motor control, appliance control and isdn or a dsl network termination. the 132 khz operation allows the use of a low cost ee13 or ef12.6 core transformer while still providing good ef? ciency. the frequency jitter in tinyswitch-ii makes it possible to use a single inductor (or two small resistors for under 3 w applications if lower ef? ciency is acceptable) in conjunction with two input capacitors for input emi ? ltering. the auto-restart function removes the need to oversize the output diode for short circuit conditions allowing the design to be optimized for low cost and maximum ef? ciency. in charger applications, it eliminates the need for a second optocoupler and zener diode for open loop fault protection. auto-restart also saves the cost of adding a fuse or increasing the power rating of the current sense resistors to survive reverse battery conditions. for applications requiring undervoltage lock out (uvlo), such as pc standby, the tinyswitch-ii eliminates several components and saves cost. tinyswitch-ii is well suited for applications that require constant voltage and constant current output. as tinyswitch-ii is always powered from the input high voltage, it therefore does not rely on bias winding voltage. consequently this greatly simpli? es designing chargers that must work down to zero volts on the output. 2.5 w cv/cc cell-phone charger as an example, figure 14 shows a tny264 based 5 v, 0.5 a, cellular phone charger operating over a universal input range (85 vac to 265 vac). the inductor (l1) forms a -? lter in conjunction with c1 and c2. the resistor r1 damps resonances in the inductor l1. frequency jittering operation of tinyswitch-ii allows the use of a simple -? lter described above in combination with a single low value y1-capacitor (c8) to meet worldwide conducted emi standards. the addition of a shield winding in the transformer allows conducted emi to be met even with the output capacitively earthed (which is the worst case condition for emi). the diode d6, capacitor c3 and resistor r2 comprise the clamp circuit, limiting the leakage inductance turn-off voltage spike on the tinyswitch-ii drain pin to a safe value. the output voltage is determined by the sum of the optocoupler u2 led forward drop (~1 v), and zener diode vr1 voltage. resistor r8 maintains a bias current through the zener diode to ensure it is operated close to the zener test current.
rev. h 02/09 8 tny263-268 www.powerint.com up undervoltage threshold is set at 200 vdc, slightly below the lowest required operating dc input voltage, for start-up at 170 vac, with doubler. this feature saves several components needed to implement the glitch-free turn-off compared with discrete or tinyswitch-ii based designs. during turn-on the recti? ed dc input voltage needs to exceed 200 v undervoltage threshold for the power supply to start operation. but, once the power supply is on it will continue to operate down to 140 v recti? ed dc input voltage to provide the required hold up time for the standby output. the auxiliary primary side winding is recti? ed and ? ltered by d2 and c2 to create a 12 v primary bias output voltage for the main power supply primary controller. in addition, this voltage is used to power the tinyswitch-ii via r4. although not necessary for operation, supplying the tinyswitch-ii externally reduces the device quiescent dissipation by disabling the internal drain derived current source normally used to keep the bypass pin capacitor (c3) charged. an r4 value of 10 k provides 600 a into the bypass pin, which is slightly in excess of the current consumption of tinyswitch-ii. the excess current is safely clamped by an on-chip active zener diode to 6.3 v. the secondary winding is recti? ed and ? ltered by d3 and c6. for a 15 w design an additional output capacitor, c7, is required due to the larger secondary ripple currents compared to the 10 w standby design. the auto-restart function limits output current during short circuit conditions, removing the need to over rate d3. switching noise ? ltering is provided by l1 and c8. the 5 v output is sensed by u2 and vr1. r5 is used to ensure that the zener diode is biased at its test current and r6 centers the output voltage at 5 v. in many cases the zener regulation method provides suf? cient accuracy (typically 6% over a 0 c to 50 c temperature range). this is possible because tinyswitch-ii limits the dynamic range of the optocoupler led current, allowing the zener diode to operate at near constant bias current. however, if higher accuracy is required, a tl431 precision reference ic may be used to replace vr1. a simple constant current circuit is implemented using the v be of transistor q1 to sense the voltage across the current sense resistor r4. when the drop across r4 exceeds the v be of transistor q1, it turns on and takes over control of the loop by driving the optocoupler led. resistor r6 assures suf? cient voltage to keep the control loop in operation down to zero volts at the output. with the output shorted, the drop across r4 and r6 (~1.2 v) is suf? cient to keep the q1 and led circuit active. resistors r7 and r9 limit the forward current that could be drawn through vr1 by q1 under output short circuit conditions, due to the voltage drop across r4 and r6. 10 and 15 w standby circuits figures 15 and 16 show examples of circuits for standby applications. they both provide two outputs: an isolated 5 v and a 12 v primary referenced output. the ? rst, using tny266p, provides 10 w, and the second, using tny267p, 15 w of output power. both operate from an input range of 140 vdc to 375 vdc, corresponding to a 230 vac or 100/115 vac with doubler input. the designs take advantage of the line undervoltage detect, auto-restart and higher switching frequency of tinyswitch-ii. operation at 132 khz allows the use of a smaller and lower cost transformer core, ee16 for 10 w and ee22 for 15 w. the removal of pin 6 from the 8 pin dip tinyswitch-ii packages provides a large creepage distance which improves reliability in high pollution environments such as fan cooled power supplies. capacitor c1 provides high frequency decoupling of the high voltage dc supply, only necessary if there is a long trace length from the dc bulk capacitors of the main supply. the line sense resistors r2 and r3 sense the dc input voltage for line undervoltage. when the ac is turned off, the undervoltage detect feature of the tinyswitch-ii prevents auto-restart glitches at the output caused by the slow discharge of large storage capacitance in the main converter. this is achieved by preventing the tinyswitch-ii from switching when the input voltage goes below a level needed to maintain output regulation, and keeping it off until the input voltage goes above the undervoltage threshold, when the ac is turned on again. with r2 and r3, giving a combined value of 2 m , the power
rev. h 02/09 9 tny263-268 www.powerint.com c1 0.01 f 1 kv 140 - 375 vdc input l1 10 h 2 a r5 680 r6 59 1% d3 1n5822 u1 tny266p c5 2.2 nf 1 kv d1 1n4005gp u2 tlp181y vr1 bzx79b3v9 5 4 2 1 10 8 tinyswitch-ii d s bp +5 v, 2 a rtn c2 82 f 35 v c8 470 f 10 v pi-2713-021809 c4 1 nf y1 d2 1n4148 en +12 vdc 20 ma 0 v c3 0.1 f 50 v r4 10 k c6 1000 f 10 v r2 1 m r3 1 m r1 200 k t1 performance summary continuous output power: 10.24 w efficiency: 75% figure 16. 15 w standby supply. c1 0.01 f 1 kv 140 - 375 vdc input l1 10 h 3 a r5 680 d3 sb540 u1 tny267p c5 2.2 nf 1 kv d1 1n4005gp u2 tlp181y performance summary continuous output power: 15.24 w efficiency: 78% 5 4 2 1 10 8 tinyswitch-ii d s bp +5 v, 3 a rtn c2 82 f 35 v c8 470 f 10 v pi-2712-021809 c4 1 nf y1 d2 1n4148 en +12 vdc 20 ma 0 v c3 0.1 f 50 v r4 10 k c7 1000 f 10 v c6 1000 f 10 v r2 1 m r3 1 m r1 100 k t1 r6 59 1% vr1 bzx79b3v9 figure 15. 10 w standby supply.
rev. h 02/09 10 tny263-268 www.powerint.com key application considerations tinyswitch-ii vs. tinyswitch table 2 compares the features and performance differences between the tny254 device of the tinyswitch-ii family with the tinyswitch-ii family of devices. many of the new features eliminate the need for or reduce the cost of circuit components. other features simplify the design and enhance performance. design output power table 1 (front page) shows the practical continuous output power levels that can be obtained under the following conditions: table 2. comparison between tinyswitch and tinyswitch-ii. *not available. ** see typical performance curves. the minimum dc input voltage is 90 v or higher for 85 vac input, or 240 v or higher for 230 vac input or 115 vac input with a voltage doubler. this corresponds to a ? lter capacitor of 3 f/w for universal input and 1 f/w for 230 vac or 115 vac with doubler input. a secondary output of 5 v with a schottky recti? er diode. assumed ef? ciency of 77% (tny267 & tny268), 75% (tny265 & tny266) and 73% (tny263 & tny264). the parts are board mounted with source pins soldered to suf? cient area of copper to keep the die temperature at or below 100 c. in addition to the thermal environment (sealed enclosure, ventilated, open frame, etc.), the maximum power capability of tinyswitch-ii in a given application depends on transformer 1. 2. 3. 4. tinyswitch-ii vs. tinyswitch function tinyswitch tny254 tinyswitch-ii tny263-268 tinyswitch-ii advantages switching frequency and tolerance temperature variation (0-100 c)** 44 khz 10% (at 25 c) +8% 132 khz 6% (at 25 c) +2%) smaller transformer for low cost ease of design manufacturability optimum design for lower cost ? ? ? ? active frequency jitter n/a* 4 khz lower emi minimizing ? lter component costs ? transformer audible noise reduction n/a* yesCbuilt into controller practically eliminates audible noise with ordinary dip varnished transformer C no special construction or gluing required ? line uv detect n/a* single resistor programmable prevents power on/off glitches ? current limit tolerance temperature variation (0-100 c)** 11% (at 25 c) -8% 7% (at 25 c) 0%) increases power capability and simpli? es design for high volume manufacturing ? auto-restart n/a* 6% effective on-time limits output short-circuit current to less than full load current no output diode size penalty protects load in open loop fault conditions no additional components required ? ? ? ? bypass pin zener clamp n/a* internally clamped to 6.3 v allows tinyswitch-ii to be powered from a low voltage bias winding to improve ef? ciency and to reduce on-chip power dissipation ? drain creepage at package 0.037 in. / 0.94 mm 0.137 in. / 3.48 mm greater immunity to arcing as a result of dust, debris or other contaminants build-up ?
rev. h 02/09 11 tny263-268 www.powerint.com core size and design (continuous or discontinuous), ef? ciency, minimum speci? ed input voltage, input storage capacitance, output voltage, output diode forward drop, etc., and can be different from the values shown in table 1. audible noise the tinyswitch-ii practically eliminates any transformer audio noise using simple ordinary varnished transformer construction. no gluing of the cores is needed. the audio noise reduction is accomplished by the tinyswitch-ii controller reducing the current limit in discrete steps as the load is reduced. this minimizes the ? ux density in the transformer when switching at audio frequencies. worst case emi & ef? ciency measurement since identical tinyswitch-ii supplies may operate at several different frequencies under the same load and line conditions, care must be taken to ensure that measurements are made under worst case conditions. when measuring ef? ciency or emi verify that the tinyswitch-ii is operating at maximum frequency and that measurements are made at both low and high line input voltages to ensure the worst case result is obtained. layout single point grounding use a single point ground connection at the source pin for the bypass pin capacitor and the input filter capacitor (see figure 17). primary loop area the area of the primary loop that connects the input ? lter capacitor, transformer primary and tinyswitch-ii together should be kept as small as possible. primary clamp circuit a clamp is used to limit peak voltage on the drain pin at turn- off. this can be achieved by using an rcd clamp (as shown in figure 14). a zener and diode clamp (200 v) across the primary or a single 550 v zener clamp from drain to source can also be used. in all cases care should be taken to minimize the circuit path from the clamp components to the transformer and tinyswitch-ii. thermal considerations copper underneath the tinyswitch-ii acts not only as a single point ground, but also as a heatsink. the hatched areas shown in figure 17 should be maximized for good heat sinking of tinyswitch-ii and the same applies to the output diode. en/uv pin if a line undervoltage detect resistor is used then the resistor should be mounted as close as possible to the en/uv pin to minimize noise pick up. the voltage rating of a resistor should be considered for the undervoltage detect (figure 15: r2, r3) resistors. for 1/4 w resistors, the voltage rating is typically 200 v continuous, whereas for 1/2 w resistors the rating is typically 400 v continuous. y-capacitor the placement of the y-capacitor should be directly from the primary bulk capacitor positive rail to the common/return terminal on the secondary side. such placement will maximize the emi bene? t of the y-capacitor and avoid problems in common-mode surge testing. optocoupler it is important to maintain the minimum circuit path from the optocoupler transistor to the tinyswitch-ii en/uv and source pins to minimize noise coupling. the en/uv pin connection to the optocoupler should be kept to an absolute minimum (less than 12.7 mm or 0.5 in.), and this connection should be kept away from the drain pin (minimum of 5.1 mm or 0.2 in.). output diode for best performance, the area of the loop connecting the secondary winding, the output diode and the output ? lter capacitor, should be minimized. see figure 17 for optimized layout. in addition, suf? cient copper area should be provided at the anode and cathode terminals of the diode for adequate heatsinking. input and output filter capacitors there are constrictions in the traces connected to the input and output ? lter capacitors. these constrictions are present for two reasons. the ? rst is to force all the high frequency currents to ? ow through the capacitor (if the trace were wide then it could ? ow around the capacitor). secondly, the constrictions minimize the heat transferred from the tinyswitch-ii to the input ? lter capacitor and from the secondary diode to the output ? lter capacitor. the common/return (the negative output terminal in figure 17) terminal of the output ? lter capacitor should be connected with a short, low impedance path to the secondary winding. in addition, the common/ return output connection should be taken directly from the secondary winding pin and not from the y-capacitor connection point. pc board cleaning power integrations does not recommend the use of no clean ? u x . for the most up-to-date information visit the pi website at: www.powerint.com.
rev. h 02/09 12 tny263-268 www.powerint.com top view pi-2707-012901 y1- capacitor opto- coupler d en/uv bp + ? hv + ? dc out input filter capacitor output filter capacitor safety spacing maximize hatched copper areas ( ) for optimum heat sinking s s sec c bp tinyswitch-ii pri t r a n s f o r m e r figure 17. recommended circuit board layout for tinyswitch-ii with undervoltage lock out resistor.
rev. h 02/09 13 tny263-268 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise speci? ed) min typ max units control functions output frequency f osc t j = 25 c see figure 4 average 124 132 140 khz peak-peak jitter 8 maximum duty cycle dc max s1 open 62 65 68 % en/uv pin turnoff threshold current i dis t j = -40 c to 125 c -300 -240 -170 a en/uv pin voltage v en i en/uv = -125 a 0.4 1.0 1.5 v i en/uv = 25 a 1.3 2.3 2.7 drain supply current i s1 v en/uv = 0 v 430 500 a i s2 en/uv open (mosfet switching) see note a, b tny263 200 250 a tny264 225 270 tny265 245 295 tny266 265 320 tny267 315 380 tny268 380 460 bypass pin charge current i ch1 v bp = 0 v, t j = 25 c see note c, d tny263-264 -5.5 -3.3 -1.8 ma tny265-268 -7.5 -4.6 -2.5 i ch2 v bp = 4 v, t j = 25 c see note c, d tny263-264 -3.8 -2.0 -1.0 tny265-268 -4.5 -3.0 -1.5 absolute maximum ratings (1,4) drain voltage .................................. ................ -0.3 v to 700 v drain peak current: tny263......................................400 ma tny264.....................................400 ma .................................... tny265......................................440 ma tny266.....................................560 ma .................................... tny267.....................................720 ma tny268.....................................880 ma en/uv voltage ....................................................... -0.3 v to 9 v en/uv current ............................................................... 100 ma bypass voltage .................................................. .. -0.3 v to 9 v storage temperature ....................................... -65 c to 150 c operating junction temperature (2) .................... -40 c to 150 c lead temperature (3) ....................................................... ..260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. maximum ratings speci? ed may be applied one at a time, without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. thermal impedance thermal impedance: p or g package: ( ja ) ........................... 70 c/w (2) ; 60 c/w (3) ( jc ) (1) ............................................... 11 c/w notes: 1. measured on the source pin close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad.
rev. h 02/09 14 tny263-268 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise speci? ed) min typ max units control functions (cont.) bypass pin voltage v bp see note c 5.6 5.85 6.15 v bypass pin voltage hysteresis v bph 0.80 0.95 1.20 v en/uv pin line under- voltage threshold i luv t j = 25 c 44 49 54 a circuit protection current limit i limit tny263 t j = 25 c di/dt = 42 ma/ s see note e 195 210 225 ma tny264 t j = 25 c di/dt = 50 ma/ s see note e 233 250 267 tny265 t j = 25 c di/dt = 55 ma/ s see note e 255 275 295 tny266 t j = 25 c di/dt = 70 ma/ s see note e 325 350 375 tny267 t j = 25 c di/dt = 90 ma/ s see note e 419 450 481 tny268 t j = 25 c di/dt = 110 ma/ s see note e 512 550 588 initial current limit i init see figure 21 t j = 25 c 0.65 x i limit(min) ma leading edge blanking time t leb t j = 25 c see note f 170 215 ns current limit delay t ild t j = 25 c see note f, g 150 ns thermal shutdown temperature 125 135 150 c thermal shutdown hysteresis 70 c output on-state resistance r ds(on) tny263 i d = 21 ma t j = 25 c 33 38 t j = 100 c 50 57 tny264 i d = 25 ma t j = 25 c 28 32 t j = 100 c 42 48 tny265 i d = 28 ma t j = 25 c 19 22 t j = 100 c 29 33
rev. h 02/09 15 tny263-268 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise speci? ed) min typ max units output (cont.) on-state resistance r ds(on) tny266 i d = 35 ma t j = 25 c 14 16 t j = 100 c 21 24 tny267 i d = 45 ma t j = 25 c 7.8 9.0 t j = 100 c 11.7 13.5 tny268 i d = 55 ma t j = 25 c 5.2 6.0 t j = 100 c 7.8 9.0 off-state drain leakage current i dss v bp = 6.2 v, v en/uv = 0 v, v ds = 560 v, t j = 125 c tny263-266 50 a tny267-268 100 breakdown voltage bv dss v bp = 6.2 v, v en/uv = 0 v, see note h, t j = 25 c 700 v rise time t r measured in a typical flyback converter application 50 ns fall time t f 50 ns drain supply voltage 50 v output en/uv delay t en/uv see figure 20 10 s output disable setup time t dst 0.5 s auto-restart on-time t ar t j = 25 c see note i 50 ms auto-restart duty cycle dc ar 5.6 % notes: total current consumption is the sum of i s1 and i dss when en/uv pin is shorted to ground (mosfet not switching) and the sum of i s2 and i dss when en/uv pin is open (mosfet switching). since the output mosfet is switching, it is dif? cult to isolate the switching current from the supply current at the drain. an alternative is to measure the bypass pin current at 6.1 v. bypass pin is not intended for sourcing supply current to external circuitry. see typical performance characteristics section for bypass pin start-up charging waveform. for current limit at other di/dt values, refer to figure 25. this parameter is derived from characterization. this parameter is derived from the change in current limit measured at 1x and 4x of the di/dt shown in the i limit speci? cation. breakdown voltage may be checked against minimum bv dss speci? cation by ramping the drain pin voltage up to but not exceeding minimum bv dss . auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). a. b. c. d. e. f. g. h. i.
rev. h 02/09 16 tny263-268 www.powerint.com figure 19. tinyswitch-ii duty cycle measurement. figure 20. tinyswitch-ii output enable timing. figure 18. tinyswitch-ii general test circuit. pi-2686-101700 0.1 f 10 v 50 v 470 5 w s2 470 note: this test circuit is not applicable for current limit or output characteristic measurements. d en/uv bp s s s s 150 v s1 2 m pi-2364-012699 en/uv t p t en/uv dc max t p = 1 f osc v drain (internal signal) 0.8 figure 21. current limit envelope.
rev. h 02/09 17 tny263-268 www.powerint.com typical performance characteristics figure 22. breakdown vs. temperature. 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c ) b rea kd own v o l tage (normalized to 25 c) pi-2213-012301 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction temperature ( c) pi-26 8 0-021 8 09 output frequency (normalized to 25 c) 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 time (ms) pi-2240-012301 bypass pin voltage (v) 7 drain voltage (v) drain current (ma) 300 250 200 100 50 150 0 0246810 t case = 25 c t case = 100 c pi-2221-032504 tny263 0.85 tny264 1.0 tny265 1.5 tny266 2.0 tny267 3.5 tny268 5.5 scaling factors: figure 23. frequency vs. temperature. figure 24. current limit vs. temperature. figure 25. current limit vs. di/dt. figure 26. bypass pin start-up waveform. figure 27. output characteristic. 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1234 normalized di/dt pi-2697-033104 normalized current limit tny263 42 ma/ s 210 ma tny264 50 ma/ s 250 ma tny265 55 ma/ s 275 ma tny266 70 ma/ s 350 ma tny267 90 ma/ s 450 ma tny268 110 ma/ s 550 ma normalized di/dt = 1 normalized current limit = 1 1 0.8 0.6 0.4 0.2 0 -50 0 50 100 150 temperature ( o c) pi-2714-021809 1.2 current limit (normalized to 25 o c) tny263/268 tny264-266 tny267
rev. h 02/09 18 tny263-268 www.powerint.com typical performance characteristics (cont.) drain voltage (v) drain capacitance (pf) pi-2683-033104 0 100 200 300 400 500 600 1 10 100 1000 tny263 1.0 tny264 1.0 tny265 1.5 tny266 2.0 tny267 3.5 tny268 5.5 scaling factors: 35 20 25 30 5 10 15 0 0 200 400 600 drain voltage (v) power (mw) pi-2225-033104 tny263 1.0 tny264 1.0 tny265 1.5 tny266 2.0 tny267 3.5 tny268 5.5 scaling factors: 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction temperature ( c) pi-2698-012301 under-voltage threshold (normalized to 25 c) figure 28. c oss vs. drain voltage. figure 29. drain capacitance power. figure 30. under-voltage threshold vs. temperature.
rev. h 02/09 19 tny263-268 www.powerint.com notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/ 8 5) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 6 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.4 8 mm). 6. lead width measured at package body. 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .00 8 (.20) .015 (.3 8 ) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .3 8 7 (9. 8 3) .240 (6.10) .260 (6.60) .125 (3.1 8 ) .145 (3.6 8 ) .057 (1.45) .06 8 (1.73) .120 (3.05) .140 (3.56) .015 (.3 8 ) minimum .04 8 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 seating plane -d- -t- p0 8 b dip- 8 b pi-2551-121504 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.4 8 ) minimum
rev. h 02/09 20 tny263-268 www.powerint.com smd- 8 b pi-2546-121504 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .3 8 7 (9. 8 3) .04 8 (1.22) .009 (.23) .053 (1.35) .032 (. 8 1) .037 (.94) .125 (3.1 8 ) .145 (3.6 8 ) -d- notes: 1. controlling dimensions are inches. millimeter sizes are shown in parentheses. 2. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. pin 6 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.4 8 mm). 5. lead width measured at package body. 6. d and e are referenced datums on the package body. .057 (1.45) .06 8 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .3 88 (9. 8 6) .137 (3.4 8 ) minimum .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g0 8 b .420 .046 .060 .060 .046 .0 8 0 pin 1 .0 8 6 .1 8 6 .2 8 6 solder pad dimensions part ordering information ? tinyswitch product family ? series number ? package identi? er g plastic surface mount smd-8b p plastic dip-8b ? lead finish blank standard (sn pb) n pure matte tin (rohs compliant) g rohs compliant and halogen free (p package only) ? tape & reel and other options blank standard con? gurations tl tape & reel, 1 k pcs minimum, g package only. tny 264 g n - tl
rev. h 02/09 21 tny263-268 www.powerint.com revision notes date aC 03/01 b corrected ? rst page spacing and sentence in description describing innovative design. corrected frequency jitter in figure 4 and frequency jitter in parameter table. added last sentence to over temperature protection section. clari? ed detecting when there is no external resistor connected to the en/uv pin. corrected figure 6 and its description in the text. corrected formatting, grammar and style errors in text and ? gures. corrected and moved worst case emi & ef? ciency measurement section. added pc board cleaning section. replaced figure 21 and smd-8b package drawing. 07/01 c corrected q ja for p/g package. updated figures 15 and 16 and text description for zener performance. corrected dip-8b and smd-8b package drawings. 04/03 d corrected en/uv under-voltage threshold in text. corrected 2 mw connected between positive dc input to en/uv pin in text and figures 15 and 16. 03/04 e added tny263 and tny265. 04/04 f added lead-free ordering information. 12/04 g 1) typographical correction in off-state drain leakage current parameter condition. 2) removed i ds condition from bv dss parameter and added new note h. 3) added note 4 to absolute maximum ratings speci? cations. 04/05 h reformatted document, updated figures 23 and 24 and part ordering information. 02/09
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power inte grations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a licens e under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in s igni? cant injury or death to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2001, power integrations, inc. 1. 2. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-021-6354-6323 fax: +86-021-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei 114, taiwan r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44-1252-730-141 fax: +44-1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 ..

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